[India] Physical Design Engineer - Hyderabad Knowledge City, India
About the role
As a Physical Design Engineer at EdgeCortix, you will contribute to the implementation of AI acceleration SoCs and chiplets, driving front-end synthesis experiments and taking IPs through the place and route flow. This role focuses on synthesis, timing analysis, floorplanning, power optimization, and design closure in collaboration with internal RTL and architecture teams as well as external implementation partners.
What you'll do
- Drive and maintain the RTL-to-GDSII flow, focusing on synthesis, STA, and design closure while accounting for DVFS and MMMC. - Define floorplans, block partitioning strategies, and clock tree implementation for hierarchical designs. - Lead STA closure across PVT corners and operating modes, optimizing physical constraints (SDC, TCL) and executing equivalence checks. - Coordinate with external vendors for backend P&R execution and review their outputs for quality, IR-drop, and EM sign-off. - Implement low-power design strategies using UPF (Unified Power Format) and drive ECO implementation based on RTL changes or timing requirements. - Evaluate standard cell libraries and implementation methodologies to improve PPA and maintain internal automation scripts.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in physical design of SoCs with a focus on synthesis and timing. - Proficiency in STA and synthesis tools such as PrimeTime, Design Compiler, or Genus. - Familiarity with backend flows and interaction with P&R teams. - Scripting skills in TCL, Python, or Shell. - Experience working with advanced technology nodes (12nm and below).
Nice to have
- Master’s degree in a relevant field. - 8–10+ years of experience in physical design or chip implementation. - Prior experience coordinating with remote backend implementation teams. - Experience in chiplet architecture or hierarchical SoC designs. - Understanding of sign-off checks (LVS, DRC), IR-drop, crosstalk, and EM analysis. - Proficiency in UPF-based low-power flows and ECO handling.
Skills: RTL-to-GDSII, synthesis, STA, design closure, floorplan
This role has been open 124 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 682 |
| Open roles in the wider Physical Implementation family | 3 | 1530 · 112 employers |
| Median days open | 124 d | 66 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDSII, synthesis, STA, design closure, floorplan
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.