[India] Physical Design Lead - Hyderabad Knowledge City, India
About the role
As the Physical Design Lead, you will own the physical implementation strategy for AI SoCs, chiplets, and IP blocks while providing technical leadership to the Physical Design team and external implementation partners. You will drive Power, Performance, and Area (PPA) optimization, implementation methodology, and design closure from RTL to GDSII.
What you'll do
- Lead the end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and hardened IP blocks, ensuring tape-out with optimal PPA. - Drive synthesis, floor planning, placement, CTS, routing, STA, timing closure, and sign-off across multiple PVT corners using Synopsys and Cadence tools. - Own power planning and analysis, including UPF implementation, power grid generation, IR-drop, EM analysis, power budgeting, and power integrity. - Develop and optimize implementation constraints (SDC, TCL), perform timing analysis, resolve timing bottlenecks, and drive ECO implementation. - Define floor planning strategies and hierarchical partitioning for complex SoCs and chiplet-based designs. - Coordinate with external backend implementation partners, review deliverables, and align execution with project milestones and quality standards.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of experience in physical design of complex SoCs with expertise in synthesis, timing closure, and physical implementation. - Proven experience in RTL-to-GDSII implementation using Synopsys and/or Cadence EDA tools. - Expertise in STA, synthesis, floorplanning, CTS, P&R, MMMC, DVFS, and low-power implementation (UPF). - Experience with advanced technology nodes (12nm and below). - Scripting skills using TCL, Python, and Shell, alongside experience working with external design service partners.
Nice to have
- Master's degree in Electrical Engineering or a related discipline. - 10–15+ years of experience in Physical Design or SoC implementation. - Experience leading physical implementation for multiple tape-outs. - Experience with AI accelerators, chiplet architectures, or hierarchical SoC designs. - Understanding of DRC/LVS, IR-drop, EM, crosstalk, and physical sign-off.
Skills: RTL-to-GDSII, PPA optimization, synthesis, floor planning, timing closure
This role has been open 89 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 682 |
| Open roles in the wider Physical Implementation family | 3 | 1530 · 112 employers |
| Median days open | 124 d | 66 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDSII, PPA optimization, synthesis, floor planning, timing closure
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.