Implementation Timing / STA Design Engineer
$140,000 - $210,000 USD yearly
Originally posted 30 April 2026 by the employer.
Join the Snapdragon SoC implementation team delivering sub-3nm designs across mobile, AI, and automotive sectors.
About the role
This role focuses on timing constraints development, power analysis, static timing analysis (STA), and timing closure within Qualcomm's SoC Implementation Team. The position supports Snapdragon SoCs fabricated in sub-3nm nodes across mobile, AI, and automotive applications.
What you'll do
- Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. - Collaborate with RTL design and physical design teams to identify timing requirements and bottlenecks. - Generate, review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. - Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing. - Analyze timing across modes and corners, applying concepts including path pessimism and margins.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 3+ years, or PhD with 2+ years). - Proficiency with tools including PrimeTime and Fishtail/TCM. - Experience with static timing analysis, timing constraints development, and timing closure. - Scripting skills in Tcl, Perl, or Python.
Skills: static timing analysis, timing closure, clock domain crossing, low-power multi-voltage, SoC cores
This role has been open 177 days — below the 178-day median for Physical Design roles.
Physical Design · Digital Backend
|
Open roles in category
38
|
Median days open
178 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (38 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 38 |
| Open roles in the wider Physical Implementation family | 171 | 1489 · 109 employers |
| Median days open | 103 d | 178 d (−75 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: static timing analysis, timing closure, clock domain crossing, low-power multi-voltage, SoC cores
Who's hiring in this category
- Micron Technology · 4 open roles · median 124 d
- Qualcomm (this employer) · 4 open roles · median 103 d
- Intel Corporation · 3 open roles · median 16 d
- SiTime · 3 open roles · median 93 d
- Altera · 2 open roles · median 220 d
- Analog Devices · 2 open roles · median 206 d
How we counted: 38 open Physical Design (Digital Backend) roles from 22 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.