IC packaging layout manager
$149,340 - $223,700 USD yearly
Leading IC packaging layout for high-speed 2D and 2.5D packages utilizing technologies like CoWOS and RDL interposers.
Originally posted 5 November 2026 by the employer.
About the role
The Manager will be responsible for managing the team involved in IC packaging layout for high-speed 2D and 2.5D packages across multiple product lines. The focus is New Product Introduction (NPI), driving semiconductor package development from concept through final package design, engineering samples, and production ramp-up.
What you'll do
- Manage and develop the engineering team responsible for IC packaging layout considering manufacturing and assembly tolerances.
- Allocate and manage layout resources across multiple product lines from concept through development and mass production.
- Oversee IC package layout for high-speed SerDes interfaces (such as 224 Gbps) as well as die-to-die and HBM interfaces in 2D and 2.5D RDL interposers.
- Drive Design for Manufacturing (DFM) processes, package substrate design rules, and assembly rules across external IC package layout vendors.
- Set up constraint manager requirements for high-speed interfaces and translate power supply requirements into power plane design.
- Automate package layout tasks using scripting and AI methodologies.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 8+ years of related experience, or a Master’s/PhD with 8-10 years of experience.
- Experience managing technical packaging layout teams.
- Strong expertise with IC package layout tools, such as Cadence APD or Mentor XPD.
- Experience with 2.5D package design for IC packaging technologies such as CoWOS.
- Experience with IC package layout for die-to-die and HBM interfaces in 2D and 2.5D RDL interposers, as well as high-speed SerDes interfaces like 224 Gbps.
- Strong understanding of the Design for Manufacturing (DFM) process, package substrate design rules, materials, and power plane design.
Skills: Cadence APD, 2.5D, CoWoS, interposer, RDL, package layout
More semiconductor jobs: Marvell Technology jobs · Advanced packaging jobs · Santa Clara jobs
This role has been open 0 days — well below the 98-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
42
|
Median days open
98 d
|
Category median salary (all employers)
$223k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (42 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 42 |
| Median days open | 44 d | 98 d (−54 d vs this employer) |
| Median salary (USD postings) | — | $223k |
Skills observed across this category: Cadence APD, 2.5D, CoWoS, interposer, RDL, package layout
Who's hiring in this category
- Marvell Technology (this employer) · 6 open roles · median 54 d
- Micron Technology · 5 open roles · median 155 d
- AMD · 4 open roles · median 48 d
- Intel Corporation · 4 open roles · median 49 d
- NVIDIA · 4 open roles · median 84 d
- Qualcomm · 4 open roles · median 120 d
How we counted: 42 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.