HSIO/DDR Bench Test Engineer - Tijuana, Baja California, Mexico
Originally posted 14 May 2026 by the employer — open 119 days.
About the role
This role is for a Post Silicon Engineering group that develops test solutions for highly integrated SOCs. The position focuses on defining and executing test methodologies and characterization of High Speed SERDES Interfaces and LP-DDR & PC-DDR Subsystem components.
What you'll do
- Define and execute development of test methodologies for High Speed SERDES Interfaces (PCIe, USB3, UFS, DP, MIPI(DSI,CSI), PLLs) and LP-DDR & PC-DDR Subsystem components.
- Develop and execute characterization plans for High Speed Interfaces to optimize design parameters and validate electrical compliance.
- Drive first silicon bring up and debug to qualify designs fabricated at external foundries.
- Perform technical data analysis of parametric performance over various operating conditions and configurations.
- Assist in hardware design and debug power integrity (PI) and signal integrity (SI) issues related to package and board design.
- Work closely with cross-functional teams such such as IC Design and Systems Engineering for chip/circuit bring up and debug.
What you'll need
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- English fluent (>95% verbal and written).
- 1 year of experience in related areas.
Nice to have
- Master's Degree in Electrical/Computer Engineering or related field.
- Understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal and semiconductor physics.
- Knowledge of High Speed test and characterization including eye diagram characteristics, differential signals, jitter analysis, signal integrity.
- Familiarity with SERDES Characterization /Validation and Transmitter, Receiver design blocks.
- Familiarity with DDR 2/3/4/5, LPDDR 2/3/4/5 protocol, timing diagrams and device specifications.
- Hands on experience with lab equipment such as Oscilloscopes, TDRs/VNAs, J-BERT.
- Experience with Python/C# for test automation.
- Familiarity with Board Design concepts (Schematic reviews, Layout best practices).
- ASIC device level characterization skills.
- System level knowledge.
Skills: High Speed SERDES, PCIe, DDR, signal integrity, bench test, characterization
This role has been open 117 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 17 | 217 |
| Median days open | 74 d | 91 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: High Speed SERDES, PCIe, DDR, signal integrity, bench test, characterization
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm (this employer) · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.