High-Speed SerDes Interface Evaluation Leader - Kodaira, Japan
Analog & Mixed-Signal Design
Originally posted 2 April 2026 by the employer — open 161 days.
About the role
This role involves leading the technical evaluation of high-speed SerDes interfaces for automotive SoCs, specifically the R-Car series.
What you'll do
- Lead technical execution of high-speed SerDes interface evaluation for automotive SoCs, covering interfaces such as PCIe, CSI, DP, UCIe, and SerDes PHY.
- Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation.
- Define evaluation strategy, organize test items, and consolidate evaluation results for stakeholders.
- Coordinate with design teams, SoC stakeholders, and IP vendors for issue triage, root-cause investigation, and countermeasure planning.
- Provide technical leadership to evaluation members, establishing clear evaluation flow and decision criteria.
What you'll need
- Hands-on experience in evaluation or verification for high-speed interfaces (e.g., SerDes, PCIe, UCIe).
- Experience in issue analysis, root-cause investigation, and countermeasure discussion based on silicon/board evaluations, signal-quality assessment, and stress testing.
- Ability to summarize results and conduct technical discussions with design teams and stakeholders.
- Knowledge/experience related to analog behavior and characteristics relevant to high-speed links (e.g., PLL/PHY, jitter, noise, SI/PI).
- Ability to collaborate technically in English with design sites and IP vendors.
Skills: PCIe, CSI, DP, UCIe, SerDes PHY, signal integrity, stress testing, analog characteristics
Market context
This role has been open 160 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 160 d | 91 d (+69 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe, CSI, DP, UCIe, SerDes PHY, signal integrity
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.