High Speed IO Analog Mixed Signal Design Engineer - CA, San Jose, United States
Originally posted 24 July 2026 by the employer.
Design high-speed memory and die-to-die PHY IP solutions spanning LPDDRx, gDDRx, and HBMx architectures.
About the role
Be part of AMD's analog/mixed signal IP design team responsible for the design and development of IOs, high speed memory (LPDDRx, gDDRx, HBMx), and die-to-die Gbps proprietary PHY IP solutions.
What you'll do
- Execute High Speed IO/SerDes AMS circuit architecture and design. - Collaborate with System/Platform and SOC architects to translate system-level specifications into AMS block and circuit-level specifications. - Author AMS block circuit and architecture technical specifications, AMS pre-silicon verification, and AMS post-silicon characterization/validation test plans. - Work with project managers, system architects, IC designers, and physical designers to deliver IP meeting schedule and technical requirements.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or related equivalent. - Experience in High Speed IO/SerDes AMS circuit architecture and design. - Experience authoring AMS circuit technical specifications, pre-silicon verification plans, and post-silicon characterization/validation test plans.
Nice to have
- Hands-on design experience in multi-Gbps serial (PCIE, USB), parallel high-bandwidth memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6), and chip-to-chip links PHY IPs. - Knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking, including mismatch mitigation, linearity, stability, low-power, and low-noise techniques. - Experience designing analog mixed-signal blocks including DLLs, phase interpolators, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, duty cycle correctors, clock and data recovery, and clock mixers. - Understanding of high-speed IO signaling topologies, link budget analysis, jitter/SNR metrics, and system-silicon co-design/co-optimizations for PPA. - Experience in FinFET advanced CMOS process nodes (16nm/7nm/3nm and below) and low power design techniques for high speed/custom digital circuits including transistor-level timing sign-off. - Proficiency with Cadence schematic capture, Virtuoso, Spectre, and/or HSPICE circuit simulation tools, with a track record of taking AMS designs to production.
Skills: High Speed IO, SerDes, LPDDRx, HBMx, PHY
This role has been open 87 days — well above the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
232
|
Median days open
76 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (232 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 232 |
| Open roles in the wider Analog & Mixed-Signal family | 35 | 1416 · 107 employers |
| Median days open | 38 d | 76 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: High Speed IO, SerDes, LPDDRx, HBMx, PHY
Who's hiring in this category
- Synopsys · 31 open roles · median 34 d
- AMD (this employer) · 27 open roles · median 38 d
- Qualcomm · 20 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Micron Technology · 14 open roles · median 57 d
- Apple · 12 open roles · median 20 d
How we counted: 232 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.