HBM SIPI, Senior Engineer - Richardson, TX, United States
Originally posted 19 October 2026 by the employer.
High Bandwidth Memory (HBM) architecture using Through Silicon Via (TSV) technology.
About the role
As an HBM SI/PI Engineer within the Heterogeneous Integration Group, you will develop SI/PI analysis for interposers, packages, and silicon channels to support HBM build sign-off. The role focuses on High Bandwidth Memory solutions utilizing Through Silicon Via (TSV) technology to stack DRAM chips with high-speed interface dies.
What you'll do
- Perform signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency-domain characterization (insertion loss, return loss, PSXT, IL-to-XT ratio) and time-domain analysis (eye diagram, BER, jitter decomposition). - Conduct mask-based timing analysis using time-domain simulations with tools such as SPICE and ADS. - Support power integrity and PDN analysis, including impedance modeling and transient response analysis. - Execute electromagnetic extraction and modeling of signal and power delivery channels across PCBs, packages, and interposers. - Automate sign-off processes and collaborate with EDA suppliers to improve tool accuracy and analysis flows.
What you'll need
- 5+ years of experience in signal integrity (SI) and power integrity (PI) modeling and analysis. - Deep understanding of SI/PI, electromagnetic and transmission line theory, and I/O design. - Experience in circuit simulation using Keysight ADS and Synopsys HSPICE. - Experience using AI/ML/LLM for productivity or efficiency.
Nice to have
- 7+ years of experience in signal integrity and power delivery network (PDN) modeling and analysis. - Experience in SI/PI modeling and analysis for 2.5D/3D advanced packaging (CoWoS, EMIB, interposer-based designs), including time-domain analysis (eye diagram, BER, jitter decomposition, PDN) and frequency-domain characterization (S-parameters, PDN impedance). - Experience with mask-based timing budget and jitter analysis using time-domain simulation (SPICE, ADS). - Experience with high-speed interfaces such as DDR, HBM, UCIe, PCIe, and SERDES. - Proficiency in EDA tools including ANSYS HFSS/SIwave, Keysight ADS, Synopsys HSPICE, and Cadence PowerSI/PowerDC.
Skills: SI/PI analysis, HBM, interposers, packages, signal integrity
This role has been open 0 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
232
|
Median days open
76 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (232 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 232 |
| Open roles in the wider Analog & Mixed-Signal family | 49 | 1412 · 107 employers |
| Median days open | 34 d | 76 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: SI/PI analysis, HBM, interposers, packages, signal integrity
Who's hiring in this category
- Synopsys · 31 open roles · median 34 d
- AMD · 27 open roles · median 38 d
- Qualcomm · 20 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Micron Technology (this employer) · 14 open roles · median 57 d
- Apple · 12 open roles · median 20 d
How we counted: 232 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.