High Speed IO Analog Mixed Signal Design Engineer - CA, San Jose, United States
Analog & Mixed-Signal Design
Originally posted 24 July 2026 by the employer.
About the role
What you'll do
- Architect and design High Speed IO/SerDes AMS circuits.
- Translate system level specifications to AMS block/circuit level specifications.
- Author AMS block circuit and architecture technical specifications, pre-silicon verification, and post-silicon characterization/validation test plans.
What you'll need
- Hand-on design experience in multi-Gbps serial (PCIE, USB) and parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6) and chip-to-chip links PHY IPs.
- Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking.
- In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.
- Solid experience designing and architecting analog mixed-signal circuit blocks including DLLs, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators.
- Solid understanding of high-speed IO signaling topologies and architectures including system-silicon co-design/co-optimizations.
- Design experience in FinFet advanced CMOS process nodes 16nm/7nm/3nm and below.
- Proficient in AMS design flows, tools, and methodologies, including Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools.
- MS or PhD in Electrical, Computer Engineering or related equivalent.
Nice to have
- Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer.
- Solid understanding of high speed IO link budget analysis and jitter/SNR metrics and design trades.
- Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers) design and analysis including transistor level timing sign-off.
- Solid understanding of power, area and performance trade-offs in mixed signal IP design.
- Track record of successfully taking AMS designs to production.
Skills: High Speed IO, SerDes, LPDDRx, HBMx, PHY
Market context
This role has been open 67 days — below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1385 · 108 employers |
| Median days open | 60 d | 76 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: High Speed IO, SerDes, LPDDRx, HBMx, PHY
Who's hiring in this category
- AMD (this employer) · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.