Originally posted 27 May 2026 by the employer. Relisted by the employer on 11 August 2026.

About the role

This role involves analog and mixed-signal circuit design and architecture within the SerDes Technology Group, developing electrical and optical transceivers in advanced CMOS PDKs.

What you'll do

- Own performance-critical analog mixed-signal circuit blocks used in SerDes, including high-speed data converters (DAC and ADC), clocking (reference clock, PLL, clock dividers, mixers, buffers, regulators, multi-phase clock generators, error detection and correction), and analog front-end circuits (pad matching networks, ESD, CTLE, linear amplifier). - Define circuit-driven micro-architectures of Tx and Rx subsystems and drive sub-block level specifications. - Own power, performance, area, and jitter budgets of analog design blocks. - Mentor sub-block owners and conduct peer reviews of design and verification results. - Work with pre-tapeout verification and post-silicon validation teams to bring up silicon and analyze silicon results.

What you'll need

- Ph.D. in Electrical Engineering or a related field, or M.S. with relevant industrial experience in optical and/or electrical transceiver design. - Strong background in ultra-high-speed electrical and/or optical PHY design. - Expertise in analog/mixed-signal circuit design and architecture.

Nice to have

- Experience designing 200G+ CMOS transceivers, with an understanding of high-speed electrical and/or optical interface requirements. - Demonstrated proficiency in hands-on circuit optimizations, including tuning for power, performance, and area at block and system levels. - Track record in silicon productization from initial design through bring-up, validation, and ramp to mass production.

Skills: SerDes, transceivers, analog/mixed-signal, high-speed data converters, PLL, optical PHY

Market context

This role has been open 149 days — well above the 71-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category

241

Median days open

71 d

Median salary

$187k

See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring

How AMD compares in High-Speed IO/SerDes Design hiring
Metric	AMD	All employers we track in this specialty (241 roles · 47 employers)
Open roles in this specialty	27	241
Open roles in the wider Analog & Mixed-Signal family	37	1435 · 106 employers
Median days open	43 d	71 d (−28 d vs this employer)
Median salary (USD postings)	—	$187k

Skills observed across this category: SerDes, transceivers, analog/mixed-signal, high-speed data converters, PLL, optical PHY

Who's hiring in this category

Synopsys · 36 open roles · median 37 d
AMD (this employer) · 27 open roles · median 42 d
Qualcomm · 21 open roles · median 66 d
Cadence Design Systems · 20 open roles · median 148 d
Micron Technology · 15 open roles · median 39 d
Apple · 9 open roles · median 25 d

How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.

High Speed DAC Design Expert - CA, San Jose, United States