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AMD

High Speed DAC Design Expert - CA, San Jose, United States

AMD Remote friendly (US, CA, San Jose, United States) Full-time 4 months ago
Analog & Mixed-Signal Design

Originally posted 27 May 2026 by the employer — open 105 days. Relisted by the employer on 11 August 2026.

About the role

This role focuses on analog/mixed-signal circuit design and architecture for high-performance electrical and optical transceivers in advanced CMOS PDKs.

What you'll do

  • Own performance-critical analog mixed-signal circuit blocks used in Serdes, such as high-speed data converters (DAC and ADC), clocking (reference clock, PLL, clock dividers, mixers, buffers, regulators, multi-phase clock generators, error detection and correction), and analog front-end circuits (pad matching networks, ESD, CTLE, linear amplifier).
  • Define circuit-driven micro-architectures of Tx and Rx subsystems and drive sub-block level specs.
  • Own power, performance, area, and jitter budgets of analog design blocks.
  • Mentor sub-block owners and conduct peer reviews of design and verification results.
  • Work with pre-tapeout verification and post-silicon validation teams to bring up silicon and analyze silicon results.

What you'll need

  • Strong background in advanced ultra-high-speed electrical and/or optical PHY design.
  • Ph.D. in Electrical Engineering or a related field or M.S. with relevant industrial experience in optical and/or electrical transceiver design.

Nice to have

  • Experience designing 200G+ CMOS transceivers, with a deep understanding of high-speed electrical and/or optical interface requirements.
  • Demonstrated proficiency in hands-on circuit optimizations, including tuning for power, performance, and area at both block and system levels.
  • Proven track record in silicon productization—from initial design through to bring-up, validation, and successful ramp to mass production.

Skills: SerDes, transceivers, analog/mixed-signal, high-speed data converters, PLL, optical PHY

Market context

This role has been open 105 days — well above the 91-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
217
Median days open
91 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How AMD compares in High-Speed IO/SerDes Design hiring
Metric AMD All employers we track in this specialty (217 roles · 44 employers)
Open roles in category 24 217
Median days open 61 d 91 d (−30 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: SerDes, transceivers, analog/mixed-signal, high-speed data converters, PLL, optical PHY

Who's hiring in this category

  • AMD (this employer) · 24 open roles · median 61 d
  • Cadence Design Systems · 19 open roles · median 153 d
  • Qualcomm · 17 open roles · median 74 d
  • Synopsys · 16 open roles · median 53 d
  • Broadcom · 11 open roles · median 142 d
  • NVIDIA · 10 open roles · median 95 d

How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.

Apply now
US, CA, San Jose, United States
Hybrid
Full-time
4 months ago

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