High Performance DSP core Implementation(Synthesis) Senior Staff Engineer - Noida, Uttar Pradesh, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves the implementation and optimization of high-performance DSP cores, focusing on physical synthesis and methodologies.
What you'll do
- Develop and optimize DSP IP (block/SoC) with a focus on high performance and low power.
- Implement and apply physical synthesis and synthesis methodologies using industry-standard tools.
- Write timing constraints for synthesis, STA, timing closure, and pipelining.
- Address timing closure for multi-clock domain designs.
- Apply MCMM synthesis and optimization techniques.
- Implement low-power designs using UPF and power optimization flows like clock gating.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 6+ years of ASIC design or related work experience, or Master's degree and 5+ years, or PhD and 4+ years.
- 12 years of hands-on experience in Synthesis and LEC.
- Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies.
- Experience with timing constraints, STA, timing closure, and pipelining for performance optimization.
- Experience in all aspects of timing closure for multi-clock domain designs.
- Familiarity with MCMM synthesis and optimization.
- Good understanding of low-power design implementation using UPF.
- Experience with scripting languages such as Perl/Python, TCL.
- Experience with power optimization flows or techniques such as clock gating.
- Proficiency in Python/Tcl.
- Familiarity with Synthesis tools (Fusion Compiler/Genus) and LEC, LP signoff tools.
- Proficiency in VLSI front-end design steps: Verilog/VHDL, Synthesis, QoR optimization, and Equivalence Checking.
Nice to have
- Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression.
Skills: Synthesis, LEC, timing constraints, timing closure, MCMM synthesis, UPF
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
601
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (601 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 112 | 601 |
| Open roles in the wider Physical Implementation family | 155 | 1388 · 105 employers |
| Median days open | 40 d | 57 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Synthesis, LEC, timing constraints, timing closure, MCMM synthesis, UPF
Who's hiring in this category
- Qualcomm (this employer) · 103 open roles · median 42 d
- Broadcom · 38 open roles · median 67 d
- NVIDIA · 38 open roles · median 48 d
- AMD · 34 open roles · median 41 d
- Synopsys · 28 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 44 d
How we counted: 601 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.