HBM SoC Physical Design Engineer - Richardson, TX, United States
Originally posted 5 June 2026 by the employer.
About the role
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the physical implementation of HBM SoC logic and base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging, assembly, and manufacturing teams to deliver PPA and signoff collateral for tape-out.
What you'll do
- Own physical implementation for SoC blocks and top-level integration, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. - Drive timing closure across multi-mode/multi-corner (MMMC) scenarios and partner with RTL, architecture, and STA teams to converge designs. - Integrate and implement complex IP such as controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, and PHY-adjacent logic with timing and power integrity. - Perform and coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff while addressing violations. - Support tape-out execution across checklists, ECO flows, and signoff reviews, and contribute to post-silicon debug by correlating silicon behavior with PD, STA, and power analysis. - Identify flow gaps and improve productivity through scripting, automation, and methodology development.
What you'll need
- Strong experience in SoC physical design implementation from netlist to GDSII on complex designs and advanced nodes. - Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent. - Solid understanding of STA fundamentals, clocking, constraints (SDC), and closure techniques including buffering, path shaping, and useful skew. - Experience with power intent and power delivery considerations, including UPF/CPF concepts, power grid planning, and power gating implications. - Familiarity with physical verification and signoff concepts including DRC, LVS, ERC, and parasitic extraction awareness.
Nice to have
- Experience with HBM / DRAM adjacent SoC designs or memory-subsystem-heavy SoCs. - Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field. - Minimum 10 years of experience in a related field. - Proven ability to mentor and develop engineers early in their careers.
Skills: physical implementation, floor-planning, placement, CTS, timing closure, DRC/LVS
This role has been open 139 days — well above the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 673 |
| Open roles in the wider Physical Implementation family | 77 | 1494 · 109 employers |
| Median days open | 93 d | 64 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical implementation, floor-planning, placement, CTS, timing closure, DRC/LVS
Who's hiring in this category
- Qualcomm · 123 open roles · median 47 d
- AMD · 64 open roles · median 27 d
- Intel Corporation · 40 open roles · median 16 d
- Synopsys · 37 open roles · median 38 d
- NVIDIA · 36 open roles · median 66 d
- Broadcom · 34 open roles · median 103 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.