HBM IO Architecture, Principal Engineer - Richardson, TX, United States
Originally posted 16 April 2026 by the employer — open 147 days.
This role focuses on HBM IO and data path architecture across multiple product generations.
About the role
This role is for a Principal Engineer in HBM IO Design Architecture, focusing on HBM IO circuits and PHY architecture.
What you'll do
- Define and own HBM IO and data path architecture across multiple product generations.
- Architect and analyze TSV-based HBM link schemes including topology, signaling strategy, and parasitic co-design.
- Define and drive HBM PHY IO training features.
- Architect high-speed IO circuits for the HBM interface die.
- Establish IO and TSV design standards and drive alignment across design, product, package, and process teams.
What you'll need
- Bachelor’s degree in Electrical Engineering or equivalent experience.
- 7+ years of hands-on experience in memory or high-speed IO design with proven silicon success.
- Deep expertise in analog and mixed-signal CMOS circuit design and simulation.
- Strong experience with high-speed IO architectures such as Rx/Tx, PLL, DLL, DCC, phase interpolators, or equalizers.
Nice to have
- Master’s degree or PhD in Electrical Engineering or related field.
- 10+ years of experience in HBM, DRAM, or advanced memory interface design.
- Patents, publications, or trade secrets in high-speed IO, TSV interfaces, or IO training.
- Experience with HBM, LPDDR, UCIe, or other JEDEC memory standards.
- Demonstrated technical leadership across multi-disciplinary, multi-generation programs.
Skills: HBM IO and data path architecture, TSV-based HBM link schemes, HBM PHY IO training features, high-speed IO circuits, analog and mixed-signal CMOS circuit design
This role has been open 141 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 115 d | 91 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: HBM IO and data path architecture, TSV-based HBM link schemes, HBM PHY IO training features, high-speed IO circuits, analog and mixed-signal CMOS circuit design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.