Hardware Engineering, Architect-17965 - Remote
Originally posted 12 July 2026 by the employer — open 60 days.
About the role
This role involves performing interconnect assessments and optimizing system performance for high-speed interfaces, focusing on signal and power integrity.
What you'll do
- Perform interconnect assessments using modeling techniques to predict channel data rates and signal margins.
- Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.
- Assess power delivery systems to optimize power integrity for supply stability and jitter minimization.
- Document findings in reports and design guidelines.
- Communicate results and insights to design teams to improve PHY design.
- Track industry developments through activities at standards committees and memory vendor roadmaps.
What you'll need
- Proven understanding of high-speed interface signaling operation, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
- Well-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
- Ability to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.
- Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
- Knowledgeable in board-level construction and on-chip IO design operation.
Skills: DDR/HBM SIPI, high-speed interface, signal integrity, power integrity, equalization, jitter
This role has been open 58 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 16 | 217 |
| Median days open | 53 d | 91 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR/HBM SIPI, high-speed interface, signal integrity, power integrity, equalization, jitter
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys (this employer) · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.