FY27 Intern - Formal Verification Engineering Internship - 6 months, Cambridge
Originally posted 28 October 2026 by the employer.
Build end-to-end formal sign-off environments for Qualcomm CPU components.
About the role
This 6-month internship focuses on developing formal verification skills alongside the CPU design team in Cambridge. You will work on formal sign-off environments and verification plans for Qualcomm CPU components.
What you'll do
- Work with the design team to understand design intent and bring up verification plans and schedules focused on end-to-end formalisation from architecture to micro-architecture.
- Define formal verification architecture for Qualcomm CPU components.
- Develop test plans and build end-to-end formal sign-off environments.
What you'll need
- Currently pursuing a Bachelor's or Master's degree in Mathematics, Science, Engineering, or a related field with relevant coursework in computer architecture and Verilog HDL design or formal methods, OR currently pursuing a PhD in Mathematics, Science, Engineering, or a related field.
- Academic coursework or background in computer architecture.
- Knowledge of Verilog HDL design or formal methods.
Skills: formal verification, test plans, Verilog HDL, CPU components
More semiconductor jobs: Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1293 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 1293 |
| Open roles in the wider Digital Design & Verification family | 388 | 3364 · 116 employers |
| Median days open | 43 d | 58 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: formal verification, test plans, Verilog HDL, CPU components
Who's hiring in this category
- Qualcomm (this employer) · 113 open roles · median 42 d
- NVIDIA · 95 open roles · median 67 d
- AMD · 90 open roles · median 58 d
- Synopsys · 74 open roles · median 43 d
- Apple · 69 open roles · median 8 d
- SiFive · 56 open roles · median 82 d
How we counted: 1293 open Design Verification (Design Verification) roles from 98 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.