FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months) - Markham, Ontario, Canada
$54,600 - $103,350 USD yearly
Originally posted 11 September 2026 by the employer.
This internship focuses on Compute DSP/AI Processor development.
About the role
This role is for an ASIC design and verification engineering intern interested in developing machine learning technologies. You will contribute to design, verification, and modelling of ASIC HW IP (blocks) and sub-systems used in machine learning end user applications.
What you'll do
- Implement modules in hardware design languages such as SystemVerilog and HLS C/C++ / SystemC.
- Implement tests at both module and sub-system levels using UVM and SystemVerilog.
- Implement reference and bus-functional models using C++, SystemC, or Python.
- Implement design/verification methodology and automation using Python, Perl, or TCL.
- Implement and debug constraints to achieve netlist synthesis and static timing closure.
- Perform power analysis to identify/fix power bugs and contribute to power modelling/reporting.
What you'll need
- Currently enrolled in a bachelor’s or master’s degree program in computer engineering, computer science, electrical engineering, or a related field.
- Availability for 16 months (May 2027 - August 2028) with an expected graduation date of November 2027 or later.
- 1 year of academic experience with programming languages such as C, C++, Python.
- Digital Logic, Digital Design, Verilog/VHDL.
Nice to have
- Relevant academic or personal project experience.
- Relevant industry experience (internship, summer work, or others).
- Computer and multimedia architecture knowledge (CPU, Bus interconnect, Audio, Display, Video, Camera, Graphics).
- Knowledge of digital design building blocks (memories, FIFOs, clock gaters, technology node standard cells) and their implementation.
- Knowledge of ASIC design and simulation tool sets (synthesis, simulator).
- Knowledge of hardware description languages (Verilog/VHDL, HLS C/C++, SystemVerilog, SystemC).
- Knowledge of verification methodology (UVM, assertions, coverage-driven constrained-random verification).
- Knowledge of scripting languages (Python, Perl, TCL, Shell).
- Knowledge of version control (ClearCase, Git).
- Significant contributions to silicon debug and analysis.
- Experience with ASIC development from specification -> microarchitecture -> RTL coding -> verification -> synthesis -> optimization -> physical design -> post-silicon debug/correlation.
Skills: Compute DSP/AI Processor, machine learning technologies, ASIC design, verification, SystemVerilog
This role has been open 45 days — well below the 89-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
507
|
Median days open
89 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (507 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 99 | 507 |
| Open roles in the wider Software, Firmware & Systems family | 708 | 6268 · 146 employers |
| Median days open | 118 d | 89 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: Compute DSP/AI Processor, machine learning technologies, ASIC design, verification, SystemVerilog
Who's hiring in this category
- Qualcomm (this employer) · 104 open roles · median 118 d
- NVIDIA · 88 open roles · median 60 d
- AMD · 32 open roles · median 110 d
- Micron Technology · 27 open roles · median 62 d
- Mobileye · 20 open roles · median 88 d
- Analog Devices · 18 open roles · median 45 d
How we counted: 507 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.