Full chip Physical verification Engineer - Hyderabad-Sattva, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role leads full chip integration and physical verification activities, focusing on 7nm and lower nodes.
What you'll do
- Develop SOC RDL for monolithic and Advanced package technologies.
- Perform full chip integration and physical verification of FPGA/SOC designs.
- Collaborate with PD, CAD, SiTech, EMIR, PKG, and EDA vendors for seamless IP integration.
- Automate integration flows to improve functional efficiency.
- Debug full chip LVS/DRC/Antenna issues with a multi-point approach and modify rule files for quicker debugging.
What you'll need
- Master's or Bachelor's Degree in Electrical/Electronic engineering with 9+ years of experience in FPGA/SOC full chip physical verification.
- Experience with PDK updates.
- Experience with RDL/Bump/Ubump development.
- Strong scripting skills in PERL/TCL/Python.
Nice to have
- Experience in bump & ubump RDL development.
- Experience in 3D integration of AoA or SSIT designs.
- Familiarity with FinFet technology DRC debugging and fixes.
- Strong debug capabilities with parasitic extraction, LVS/DRC, and other Physical verification checks.
- Knowledge of scripting languages like SKILL.
- Knowledge of hierarchical layout handling including macros and full chip.
- Knowledge in PDK (DRC/LVS rule files).
Skills: full chip physical verification, LVS/DRC/Antenna issues, PDK updates, RDL/Bump/Ubump development, FinFet technology, automation of integration flows
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
601
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (601 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 601 |
| Open roles in the wider Physical Implementation family | 62 | 1388 · 105 employers |
| Median days open | 28 d | 57 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: full chip physical verification, LVS/DRC/Antenna issues, PDK updates, RDL/Bump/Ubump development, FinFet technology, automation of integration flows
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- Broadcom · 38 open roles · median 67 d
- NVIDIA · 38 open roles · median 48 d
- AMD (this employer) · 34 open roles · median 41 d
- Synopsys · 28 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 44 d
How we counted: 601 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.