Full-Chip Physical Design Verification Engineer - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 1 May 2026 by the employer.
RISC-V CPU and SoC physical verification closure across 7nm, 5nm, and 3nm process nodes.
About the role
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and physical verification closure across advanced technology nodes. The position focuses on physical verification for RISC-V CPU and SoC designs through tapeout.
What you'll do
- Drive full-chip signoff and lead physical verification closure including DRC, LVS, and ERC. - Debug physical verification issues using standard industry PV tools. - Collaborate across RTL, PD, CAD, packaging, and foundry teams to achieve successful tapeouts. - Drive signoff through complex verification flows and build scalable PV methodologies and automation.
What you'll need
- BS or MS in Electrical Engineering, Electronics Engineering, or a related field with 7–14 years of hands-on CPU, IP, or SoC physical verification experience. - Expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows such as Calibre, ICV, Pegasus, FC, or Innovus. - Experience in ESD planning, padring integration, bump/RDL strategies, and reliability analysis including IR drop and EM. - Understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges. - Scripting proficiency in Python and TCL for automation and flow optimization.
Skills: full-chip signoff, DRC, LVS, physical verification, advanced technology nodes
This role has been open 176 days — well above the 65-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 673 |
| Open roles in the wider Physical Implementation family | 12 | 1489 · 109 employers |
| Median days open | 176 d | 65 d (+111 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: full-chip signoff, DRC, LVS, physical verification, advanced technology nodes
Who's hiring in this category
- Qualcomm · 124 open roles · median 48 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 17 d
- Synopsys · 37 open roles · median 39 d
- NVIDIA · 36 open roles · median 67 d
- Broadcom · 35 open roles · median 104 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.