Formal Verification Engineer - New College Grad 2027 - CA, Santa Clara, United States
$100,000 - $189,750 USD yearly
Originally posted 27 October 2026 by the employer.
About the role
As a Formal Verification Engineer at NVIDIA, you will own the formal verification of RTL units for chip designs.
What you'll do
- Develop comprehensive formal verification testplan documents and identify key DUT behaviors. - Build verification environments, including environment assumptions, assertions, and cover properties based on the verification plan. - Apply formal verification techniques to prove the correctness of digital designs. - Debug RTL to identify and analyze failure scenarios. - Develop scripts to automate the formal verification process. - Review formal setups and proofs with design and verification teams.
What you'll need
- BS or MS in CS, CE, EE, Mathematics, or equivalent experience. - Knowledge or experience in formal verification techniques and abstraction techniques. - Knowledge of CPU and GPU architectures alongside digital logic fundamentals. - Hands-on experience with HDLs such as Verilog or SystemVerilog, with the ability to understand RTL. - Understanding of temporal logic assertions. - Experience with formal verification tools such as Jasper, IFV, SMV, or SPIN.
Skills: Formal Verification, SystemVerilog, RTL, assertions, Jasper
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 95 | 1277 |
| Open roles in the wider Digital Design & Verification family | 234 | 3383 · 116 employers |
| Median days open | 65 d | 64 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Formal Verification, SystemVerilog, RTL, assertions, Jasper
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA (this employer) · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.