Experienced PCIe System Design Engineer - Kfar Saba, Israel
SanDisk
Kfar Saba, Israel
Full-time
4 months ago
Analog & Mixed-Signal Design
Originally posted 21 June 2026 by the employer — open 81 days.
About the role
This role focuses on the design, implementation, and silicon validation of PCIe interfaces within SoCs.
What you'll do
- Define and implement PCIe Controller and PHY IP.
- Implement PCIe-specific features like DOE, IDE, and MFND/SR-IOV.
- Integrate PCIe/PHY IPs into the SoC fabric and define/implement Control and Status Registers (CSRs) for hardware-firmware interaction.
- Design power management mechanisms (ASPM, L1 Substates) and system-level reset sequences.
- Perform PCIe link bring-up on silicon, test connectivity, and optimize the data path.
- Troubleshoot multi-discipline complex issues using advanced AI debug tools, protocol analyzers, and oscilloscopes.
What you'll need
- 7+ years of experience as a System/Design/Validation Engineer with a strong focus on PCIe.
- Deep expertise in PCIe Gen 4/5 standards.
- Technical knowledge of NVMe protocol (Queue management, Admin/IO commands).
- Hands-on experience with PCIe protocol analyzers and high-speed oscilloscopes.
- Proficient in Python/C for test automation and hardware debugging.
- B.Sc. in Electrical Engineering or Computer Engineering.
Skills: PCIe Gen 4/5/6, NVMe, protocol layers, PHY IP, silicon bring-up, high-speed connectivity
Market context
This role has been open 56 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 5 | 217 |
| Median days open | 29 d | 91 d (−62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe Gen 4/5/6, NVMe, protocol layers, PHY IP, silicon bring-up, high-speed connectivity
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.