Ethernet Scale-Up RTL Lead/Principal Engineer
TYLsemi
San Jose, CA, United States
Full-time
5 hours ago
Digital Design & SoC Architecture
Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics.
About the role
What you'll do
- Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics.
- Lead development of high-performance Ethernet Subsystem microarchitectures including RDMA, packet processing, network offload, traffic management, congestion control, and reliability mechanisms.
- Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production.
- Optimize performance, latency, scalability, power, and reliability for demanding AI and HPC workloads.
- Collaborate across hardware, firmware, software, and system teams to deliver AI networking solutions.
- Serve as a technical leader, influencing product strategy, roadmap, and architectural direction.
What you'll need
- 15+ years of ASIC/SoC architecture and design experience.
- Proven track record delivering networking, NIC, switch, DPU, accelerator interconnect, or high-speed connectivity silicon.
- Deep expertise in SystemVerilog/RTL design and high-performance datapath architecture.
- Strong knowledge of Ethernet, RDMA, traffic management, congestion control, and scalable fabric architectures.
- Experience across the full ASIC lifecycle, from architecture to production silicon.
Nice to have
- Ultra Ethernet, UALink, RoCEv2, InfiniBand
- PCIe Gen6/Gen7, UCIe, CXL
- AI/HPC interconnects and collective communication acceleration
- 400G/800G/1.6T Ethernet systems
- High-speed SerDes and advanced networking architectures
More semiconductor jobs: RTL design jobs · San Jose jobs
Market context
This role has been open 73 days — slightly above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 1096 |
| Open roles in the wider Digital Design & Verification family | 22 | 3525 · 120 employers |
| Median days open | 76 d | 64 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.