ENGR PRIN, DESIGN LAYOUT; DSGN - Bangalore, Karnataka, India
Originally posted 9 September 2026 by the employer — open 1 day.
Join our Image Sensor team focusing on analog and mixed-signal layout design.
About the role
This role involves leading physical layout implementation for complex analog and mixed-signal blocks within the Image Sensor team. You will drive layout activities from floorplanning through verification and final signoff for product generations.
What you'll do
- Lead physical layout implementation of complex analog and mixed-signal blocks such as ADCs, PLLs, Bandgaps, References, LDOs, Bias circuits, and image sensor-related analog IPs.
- Independently own block-level layout activities from floorplanning through verification and final signoff.
- Drive layout architecture discussions, floorplanning strategies, matching requirements, power planning, shielding, and area optimization.
- Ensure high-quality execution through DRC, LVS, ERC, EM/IR, density, reliability, and other tapeout quality checks.
- Collaborate closely with circuit designers to optimize performance, area, and schedule.
- Mentor junior layout engineers and provide technical guidance on best practices and layout methodologies.
What you'll need
- 12-15 years experience in analog layout design.
- Strong hands-on experience with Cadence Virtuoso.
- Expertise in physical verification flows.
- Solid understanding of device matching and common-centroid techniques.
- Solid understanding of symmetry and critical analog routing.
- Solid understanding of shielding and noise isolation.
- Solid understanding of power planning and substrate management.
- Solid understanding of ESD and reliability considerations.
- Proven ability to independently handle complex analog layout blocks and drive closure.
Skills: analog layout design, Cadence Virtuoso, DRC LVS, physical verification, power planning
This role has been open 1 day — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
615
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (615 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 615 |
| Open roles in the wider Physical Implementation family | 7 | 1427 · 104 employers |
| Median days open | 61 d | 57 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: analog layout design, Cadence Virtuoso, DRC LVS, physical verification, power planning
Who's hiring in this category
- Qualcomm · 99 open roles · median 34 d
- NVIDIA · 42 open roles · median 49 d
- Broadcom · 41 open roles · median 59 d
- AMD · 32 open roles · median 46 d
- Synopsys · 28 open roles · median 62 d
- Intel Corporation · 25 open roles · median 61 d
How we counted: 615 open Physical Design (Physical Design) roles from 74 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.