Engineer, Design - Tempe, AZ, United States
Originally posted 12 October 2026 by the employer.
Design laminate (BGA) and wafer-level semiconductor packages balancing thermal, mechanical, and electrical requirements.
About the role
This role is responsible for developing IC package designs, creating detailed engineering drawings, and supporting design-related activities within the Design Center. The engineer develops laminate (BGA) and wafer-level packages balancing thermal, mechanical, electrical, and manufacturing requirements.
What you'll do
- Design laminate (BGA) and wafer-level semiconductor packages, including determination of design rules, optimization, verification, and package selection. - Create accurate and detailed engineering drawings with minimal supervision. - Analyze and resolve design challenges and customer-related technical issues using sound engineering principles. - Identify opportunities to improve design methodologies, processes, and technologies. - Interface with internal teams, Product Groups, Sales, and external customers to support design reviews, technical discussions, and project execution. - Prepare technical documentation and maintain accurate engineering records.
What you'll need
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, or a related engineering discipline. - Experience using CAD or similar engineering software to create and maintain technical drawings. - Ability to manage multiple tasks and complete assignments effectively with minimal supervision. - Demonstrated ability to meet project deadlines and manage priorities.
Nice to have
- Experience in semiconductor packaging design. - Experience using package design and simulation tools such as Cadence APD, Cadence Sigrity, Siemens Expedition, Ansys HFSS, and CAM350. - PCB design experience. - Working knowledge of Geometric Dimensioning and Tolerancing (GD&T) practices. - Signal Integrity (SI) and Power Integrity (PI) analysis experience.
Skills: BGA, Cadence APD, package design, SI/PI, laminate
This role has been open 0 days — well below the 57-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
220
|
Median days open
57 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amkor | All employers we track in this specialty (220 roles · 42 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 220 |
| Open roles in the wider Process, Fab & Equipment family | 51 | 10278 · 109 employers |
| Median days open | 0 d | 57 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: BGA, Cadence APD, package design, SI/PI, laminate
Who's hiring in this category
- Renesas Electronics · 31 open roles · median 37 d
- Infineon Technologies · 25 open roles · median 36 d
- Micron Technology · 20 open roles · median 77 d
- onsemi · 16 open roles · median 33 d
- Skyworks · 12 open roles · median 10 d
- Intel Corporation · 11 open roles · median 112 d
How we counted: 220 open Packaging Engineering (Packaging) roles from 42 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.