Lead Emulation Test Engineer
$180,000 - $300,000 USD yearly
This role focuses on pre-silicon validation of AI inference ASIC on the Cadence Palladium platform.
About the role
As Emulation Test Engineer, you will provide technical direction for pre-silicon validation of Positron's AI inference ASIC. You will own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and driving the "left-shift" of software development.
What you'll do
- Lead the partitioning and compilation of the design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
- Create and maintain hybrid emulation and co-simulation environments (using SCE-MI or DPI) for software teams to boot OS images and run AI workloads on pre-silicon hardware.
- Design and execute comprehensive emulation test plans to verify high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and complex AI memory hierarchies.
- Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks.
- Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage Palladium Z3 capabilities.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
- 8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations.
- Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3), including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows.
- Mastery of SystemVerilog, Verilog, and C/C++ for transactor development and reference modeling.
- Deep understanding of data center protocols including PCIe, DDR and AMBA AXI/NoC.
- Expert-level Python, Tcl, and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions.
- Proficiency in debugging low-level firmware and kernel-level issues using Verdi, SimVision, and hardware-software co-debug tools.
Skills: emulation, hardware systems, AI inference, ASIC, verification
More semiconductor jobs: Verification engineer jobs
This role has been open 104 days — well above the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Positron AI | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1345 |
| Open roles in the wider Digital Design & Verification family | 7 | 3525 · 120 employers |
| Median days open | 86 d | 58 d (+28 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: emulation, hardware systems, AI inference, ASIC, verification
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.