Emulation Lead/Principal Engineer
Create scalable pre-silicon environments for purpose-built connectivity chiplets for HPC/rack-scale AI systems.
About the role
This role involves building the platform that brings silicon to life before tapeout, creating scalable pre-silicon environments that enable firmware, software, and system validation. You will build production-grade platforms for purpose-built connectivity chiplets for HPC/rack-scale AI systems, accelerating product readiness.
What you'll do
- Architect and deploy full-chip, multi-die, and subsystem emulation environments using Palladium, ZeBu, Veloce, or similar platforms.
- Enable pre-silicon bring-up of boot ROM, firmware, drivers, operating systems, and application workloads.
- Develop scalable emulation methodologies and reusable infrastructure.
- Drive system-level validation, performance analysis, and root-cause debug across RTL, firmware, software, and verification.
- Build automation, CI/CD workflows, regressions, and release processes that scale across engineering teams.
- Lead complex debug spanning RTL, firmware, software, and hardware platforms.
What you'll need
- 10+ years of ASIC/SoC development experience with significant emulation ownership.
- Expertise with commercial emulation platforms (Palladium, ZeBu, or Veloce).
- Strong RTL skills in Verilog/SystemVerilog.
- Experience with firmware bring-up, embedded processors, interrupts, and system debug.
- Proficiency in C/C++ and scripting with Python.
- Proven track record leading complex verification and emulation programs.
Nice to have
- Ethernet, PCIe, CXL or high-speed interconnects.
- FPGA prototyping (Protium, HAPS, etc.).
- Security architectures, Root of Trust, and secure boot.
- First-silicon bring-up and system qualification experience.
Skills: emulation environments, Palladium, ZeBu, Veloce, pre-silicon bring-up, system-level validation
More semiconductor jobs: Verification engineer jobs · San Jose jobs
This role has been open 79 days — well above the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 1345 |
| Open roles in the wider Digital Design & Verification family | 22 | 3525 · 120 employers |
| Median days open | 76 d | 58 d (+18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: emulation environments, Palladium, ZeBu, Veloce, pre-silicon bring-up, system-level validation
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.