Emulation Engineer (2026 New College Graduate) - Richardson, Texas, United States of America, United States
$98,000 - $170,000 USD yearly
Originally posted 15 June 2026 by the employer.
Support hardware emulation for complex CPU, IP, and SoC designs across Veloce, ZeBu, and Palladium platforms.
About the role
This role supports hardware emulation for complex CPU, IP, and SoC designs by building and optimizing emulation environments, executing tests, and triaging failures.
What you'll do
- Build and configure designs for hardware emulation, execute directed and regression tests, identify points of failure, capture waveforms and logs, and perform initial failure triage. - Develop, improve, and maintain emulation testbench components, including custom IP, acceleration verification IP (AVIP), transactors, monitors, and supporting infrastructure. - Partner with design, architecture, verification, software, and emulation teams to reproduce issues, isolate root causes, and support debug of CPU, IP, integration, synthesis, and platform failures. - Develop and maintain scalable scripts, build flows, and automation across product lines to improve emulation setup, execution, reporting, and turnaround time. - Apply emulation architecture and platform capabilities to optimize debugging strategies, build quality, compile time, capacity, and resource utilization. - Document emulation environments, test results, failure signatures, and debug findings to support technical reviews and repeatable engineering workflows.
What you'll need
- Graduating with a Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, Computer Science, or related field with at least an overall 3.0 GPA. - Academic, internship, project, or practical experience with hardware emulation, digital design verification, FPGA prototyping, or related CPU/SoC development workflows. - Experience with or exposure to hardware emulation platforms such as Veloce, ZeBu, Palladium, or similar systems. - Scripting skills using Python, Tcl, Bash, Make, or related automation languages and build tools. - Debugging skills across CPU-internal issues, integration failures, emulator configuration or synthesis issues, scripting errors, and Linux software environments. - English fluency (written and verbal).
Nice to have
- Prior related internship or co-op experience. - Understanding of SoC and IP integration, including interconnects, bridges, tie-offs, memory-mapped registers, clocks, resets, and related system-level interfaces. - Experience with RISC-V assembly and computer architecture concepts. - Knowledge of AMBA interconnect protocols such as AHB, APB, or AXI. - Experience with the Linux kernel, Linux-based development environments, and revision-control systems such as Perforce or Git.
Skills: emulation, Veloce, Zebu, Palladium, scripting, debugging
This role has been open 122 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1241 |
| Open roles in the wider Digital Design & Verification family | 43 | 3298 · 115 employers |
| Median days open | 108 d | 65 d (+43 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: emulation, Veloce, Zebu, Palladium, scripting, debugging
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.