Originally posted 29 September 2026 by the employer.
About the role
This role involves developing and automating workflows for power semiconductor module simulation and engineering automation. It focuses on defining standardized inputs, outputs, and KPI extraction logic to orchestrate and scale simulation across engineering teams and products.
What you'll do
- Own hands-on simulation execution for power module characterization across electrical, thermal, and mechanical domains using tools such as Ansys Discovery, Q3D, HFSS, IcePak, Mechanical, OptiSLang, Cadence Virtuoso, Spectre, Calibre (DRC/LVS/PEX), SIMetrix/SIMPLIS, and PLECS.
- Define and validate KPI extraction logic from raw simulation outputs, including loop inductance, on-resistance (RDS(on)), switching energy, junction temperature (Tj,max), thermal resistance (Rth), and power-cycling lifetime.
- Design standardized, parameterized test-bench definitions and post-processing rules that convert raw tool outputs into compliance-ready KPI values.
- Document tool-specific configuration, input/output file schemas, and scripting hooks (Python, tool APIs, batch/command-line modes) for automated configuration, dispatch, and result ingestion.
- Partner with software and SDET engineers to build and validate simulation regression pipelines, ensuring automated runs reproduce trusted, manually-derived golden results.
- Research, evaluate, and prototype custom or open-source alternatives to commercial EDA tools where per-seat licensing or concurrency limits throttle agentic, parallelized simulation throughput.
What you'll need
- 3 to 5 years of hands-on experience running simulations for power semiconductor or power module design, with practical use of at least two or three of: Ansys Discovery, Q3D, HFSS, IcePak, Mechanical, Cadence Virtuoso, Spectre, Calibre, SIMetrix/SIMPLIS, or PLECS.
- Solid understanding of power module electrical, thermal, and mechanical characterization and KPIs such as parasitics, loop inductance, resistance, thermal resistance, and junction temperature.
- Practical experience configuring simulation inputs (parameters, test benches, boundary conditions) and interpreting/post-processing raw simulation outputs into engineering KPIs.
- Scripting ability in Python sufficient to automate tool configuration, batch execution, and output parsing.
- Working knowledge of GDS/layout-based design flows and how layout, parasitic extraction, and model generation feed downstream simulation.
- Ability to translate tribal SME knowledge into clear, documented, repeatable procedures that a software or AI agent engineer can implement.
Skills: EDA tools, simulation automation, electrical, thermal, mechanical simulations, Ansys, Cadence Virtuoso
This role has been open 1 day — well below the 82-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
82 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (692 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 692 |
| Open roles in the wider Physical Implementation family | 8 | 1419 · 109 employers |
| Median days open | 80 d | 82 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: EDA tools, simulation automation, electrical, thermal, mechanical simulations, Ansys, Cadence Virtuoso
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 161 d
- Synopsys · 53 open roles · median 47 d
- NVIDIA · 42 open roles · median 74 d
- Micron Technology · 41 open roles · median 109 d
- Qualcomm · 35 open roles · median 68 d
- GlobalFoundries · 27 open roles · median 49 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.