$140,000 - $210,000 USD yearly
Originally posted 11 May 2026 by the employer.
About the role
Qualcomm Technologies Inc's Global CAD team develops tools, flows, and methodologies for different aspects of VLSI design. This position focuses on developing CAD tools used in emulation, addressing synthesis, partitioning, place and route, and clock optimization.
What you'll do
- Develop emulation CAD algorithms that address Qualcomm SoC needs, including synthesis, partitioning, place and route, and clock optimization. - Work with industry-standard tools and technologies to develop solutions for infrastructure needs. - Drive compute and storage optimization across emulation workflows. - Mentor and lead other members of the engineering team.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field.
Nice to have
- Master's or PhD in Computer Science or Computer Engineering. - 2 years of ASIC design, FPGA design, verification, or related work experience. - 2 years of C SW development, CAD tool development, or related work experience. - 2 years of hands-on experience with Linux. - 2 years of direct hands-on experience with CAD SW development, with knowledge of software design principles, practices, and patterns. - Demonstrable knowledge of data structures, algorithms, and design patterns. - Experience in RTL Synthesis (System Verilog -> Netlist), Clock Tree Optimization, and exposure to VLSI design concepts and logic design. - Experience with Git, LSF, JIRA, GCC, and related technologies.
Skills: CAD tool development, C++ SW development, RTL Synthesis, VLSI design concepts, Linux
This role has been open 200 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 696 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 76 d | 71 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: CAD tool development, C++ SW development, RTL Synthesis, VLSI design concepts, Linux
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 152 d
- Synopsys · 62 open roles · median 43 d
- Micron Technology · 44 open roles · median 52 d
- GlobalFoundries · 39 open roles · median 26 d
- Qualcomm (this employer) · 39 open roles · median 76 d
- Keysight Technologies · 34 open roles · median 79 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.