Distinguished Power Architect
$279,500 - $419,500 USD yearly
This role focuses on power modeling, analysis, and optimization across CPU, AI accelerator, memory, I/O, and interconnect designs.
About the role
This role drives power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs. The position works across architecture, microarchitecture, RTL, implementation, firmware, validation, and silicon.
What you'll do
- Define power targets, budgets, operating points, and optimization strategies for CPU, AI accelerator, and SoC blocks.
- Develop and maintain architectural, activity-based, RTL, gate-level, emulation, and silicon power models.
- Set up and run RTL- and gate-level power analysis, develop benchmarks and tests, and review results for opportunities at the architecture, RTL, synthesis, and implementation levels.
- Characterize CPU, memory, PCIe, networking, storage, AI training, and AI inference workloads to identify power and performance bottlenecks.
- Drive power/performance/area/thermal tradeoff studies and power convergence across design & implementation phases.
- Develop automation, data-processing flows, dashboards, and analysis scripts using Python, TCL, Perl, or similar languages.
- Drive power-management techniques including clock gating, power gating, DVFS, adaptive voltage scaling, retention, low-power modes, and workload-aware power management.
What you'll need
- Experience in semiconductor power analysis, modeling, optimization, power management, workload characterization, or silicon validation.
- Strong understanding of CMOS power fundamentals and power-reduction techniques.
- Knowledge of CPU, AI accelerator, memory, I/O, interconnect, and processor workload behavior.
- Experience with RTL and gate-level power-analysis tools and methodologies; familiarity with tools such as Spyglass, Power Artist, Joules, PrimePower, or equivalent.
- Experience with emulation, FPGA, silicon measurement, telemetry, or power/performance correlation.
- Strong programming and scripting skills in Python; Tcl, Perl, C/C++, shell, SQL, or data-analysis tools are helpful.
Nice to have
- Experience with voltage-frequency characterization, AVS, silicon binning, SKU definition, or Power-management firmware is a plus.
- Experience using AI for productivity in silicon design.
- Bachelors degree in Electrical Engineering, Computer Engineering, or related field of study & 15 years of related experience; or Master's degree & 12 years; or PhD & 8 years.
Skills: power architect, power modeling, power analysis, CPU, AI accelerator, RTL
More semiconductor jobs: SoC design jobs · Santa Clara jobs
This role has been open 24 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 485 |
| Open roles in the wider Digital Design & Verification family | 26 | 3525 · 120 employers |
| Median days open | 24 d | 79 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: power architect, power modeling, power analysis, CPU, AI accelerator, RTL
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.