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Upscale AI

Distinguished Engineer, SerDes Clocking

Upscale AI US - Santa Clara, CA, United States Full-time 3 days ago
Analog & Mixed-Signal Design

$313,000 - $353,000 USD yearly

Originally posted 27 October 2026 by the employer.

About the role

Upscale AI is hiring a Distinguished Engineer, SerDes Clocking to work on high-performance infrastructure for artificial intelligence workloads. The role focuses on first-principles engineering across silicon, systems, and networking.

What you'll do

  • Drive technical direction and architecture for SerDes clocking across silicon and systems.
  • Execute first-principles engineering on high-performance infrastructure targeting demanding AI workloads.
  • Own foundational technical problems across silicon, systems, and networking with a focus on performance, scale, and execution.

What you'll need

  • Deep technical expertise in SerDes clocking architectures and circuit implementation.
  • Extensive background in silicon design for high-performance computing or networking systems.
  • Demonstrated technical rigor and ownership across complex silicon and system-level architectures.

Skills: SerDes, clocking, AI infrastructure

More semiconductor jobs: Signal integrity jobs · California jobs

Market context

This role has been open 1 day — well below the 72-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
244
Median days open
72 d
Category median salary (all employers)
$200k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Upscale AI compares in High-Speed IO/SerDes Design hiring
Metric Upscale AI All employers we track in this specialty (244 roles · 48 employers)
Open roles in this specialty 9 244
Open roles in the wider Analog & Mixed-Signal family 10 1536 · 106 employers
Median days open 6 d 72 d (−66 d vs this employer)
Median salary (USD postings) — $200k

Skills observed across this category: SerDes, clocking, AI infrastructure

Who's hiring in this category

  • Synopsys · 34 open roles · median 39 d
  • AMD · 28 open roles · median 46 d
  • Cadence Design Systems · 21 open roles · median 143 d
  • Qualcomm · 19 open roles · median 72 d
  • Micron Technology · 13 open roles · median 44 d
  • Apple · 9 open roles · median 27 d

How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.

Apply now
US - Santa Clara, CA, United States
On-site
Full-time
$313,000 - $353,000 USD yearly
3 days ago

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