Distinguished Circuit Engineer
$279,500 - $440,000 USD yearly
About the role
This role leads Ampere’s High-Speed I/O (HSIO) and SerDes technical direction, balancing custom in-house IP development with technical engagements alongside third-party IP vendors and foundries. You will own the technical roadmap for high-speed interfaces—including Die-to-Die (D2D), memory, and standard peripheral IOs—on 3nm, 2nm, and beyond process nodes.
What you'll do
- Architect, specify, and guide the design and execution of proprietary custom SerDes and D2D PHY macros tailored to system requirements.
- Serve as the primary technical interface with external IP vendors and foundries, evaluating offerings, driving spec modifications, conducting risk assessments, and leading make-vs-buy decisions.
- Define IP electrical, functional, and timing specifications in collaboration with SoC architects, package design, SI/PI, and logic/DV teams for server SoC integration.
- Guide analog and mixed-signal circuit architectures, including TX/RX front-ends, clock generation/distribution (PLLs, reference clocks), equalization (DFE/CTLE), and calibration engines.
- Define post-silicon validation, characterization, and lab test methodologies, leading bring-up, BER analysis, eye-centering, and root-cause debugging for complex silicon and interconnect issues.
- Partner with product and test engineering to establish HTOL, PVT validation, and production screening flows for volume manufacturing.
What you'll need
- Bachelor's degree in Electrical or Computer Engineering with 15 years of related experience, Master's with 12 years, or PhD with 8 years.
- Experience in a Principal, Fellow, or Distinguished technical leadership capacity focusing on high-speed SerDes / mixed-signal PHY silicon development.
- Silicon track record taking high-speed SerDes (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) from concept to high-volume production in advanced FinFET/GAA process nodes.
- Deep expertise in analog and mixed-signal design concepts (TX/RX front-ends, PLL/clock generation and distribution, equalizers/DFE, CDR, ADC/DAC-based SerDes) and device physics across PVT corners.
- Hands-on experience with high-speed post-silicon validation and lab measurement instruments (real-time/sampling scopes, BERTs, VNAs).
- Proficiency with EDA environments including Cadence Virtuoso, Spectre/CustomSim, or Synopsys PrimeSim/FineSim, alongside standard extraction and physical verification flows.
Skills: SerDes, PHY, mixed-signal, PAM4, D2D, Virtuoso
More semiconductor jobs: Signal integrity jobs · Santa Clara jobs
This role has been open 13 days — well below the 65-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
256
|
Median days open
65 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (256 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 256 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1541 · 115 employers |
| Median days open | 8 d | 65 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Skills observed across this category: SerDes, PHY, mixed-signal, PAM4, D2D, Virtuoso
Who's hiring in this category
- Synopsys · 39 open roles · median 37 d
- AMD · 22 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 152 d
- NVIDIA · 17 open roles · median 213 d
- Qualcomm · 16 open roles · median 86 d
- Apple · 11 open roles · median 2 d
How we counted: 256 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.