Director Post-Si Electrical Validation Engineering
$210,000 - $275,000 USD yearly
Originally posted 7 November 2026 by the employer.
About the role
Astera Labs is seeking a Director of Post-Si Electrical Validation Engineering to lead the development, bring-up, and validation of ASIC SerDes and PCIe PHY products.
What you'll do
- Lead ASIC electrical-level (PHY) validation strategy across product definition, architecture, PCB and test fixture development, automation, bring-up, debug, optimization, qualification, and production release.
- Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP.
- Direct ASIC power-on and bring-up, silicon/PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions.
- Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above.
- Partner with ASIC, system validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams.
- Build, mentor, and develop the validation engineering team while establishing ownership, technical standards, and execution mechanisms.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- Hands-on technical leadership experience in ASIC electrical-level (PHY) post-silicon validation.
- Deep expertise in high-speed NRZ and PAM4 SerDes validation and protocols, including PCIe Gen 3 and above.
- Practical experience directing silicon bring-up, debug, PVT characterization, and margin analysis.
- Experience with validation automation, test equipment, bench sockets, RF cables, and test fixtures.
More semiconductor jobs: Astera Labs jobs · Silicon validation jobs · San Jose jobs
This role has been open 0 days — well below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
130
|
Median days open
64 d
|
Category median salary (all employers)
$190k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (130 roles · 34 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 130 |
| Open roles in the wider Silicon Validation & Test family | 19 | 2394 · 121 employers |
| Median days open | 50 d | 64 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $190k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 50 d
- AMD · 16 open roles · median 76 d
- NVIDIA · 14 open roles · median 89 d
- Graphcore · 9 open roles · median 143 d
- Arm Holdings · 8 open roles · median 10 d
- Micron Technology · 6 open roles · median 215 d
How we counted: 130 open Post-Silicon Validation (Design Verification) roles from 34 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.