Director High Speed IO Architecture & Design
Originally posted 29 October 2026 by the employer.
About the role
Lead a hardware and digital IP design engineering team collaborating across AMD and partners to develop high-speed I/O technologies.
What you'll do
- Lead and manage a team of system, digital hardware, and front-end/RTL/logic designers developing reusable IP for multi-product roadmaps.
- Collaborate with IP, subsystem, and SoC architects to translate high-level requirements into microarchitecture and design implementation plans.
- Contribute to the definition of IP architecture, microarchitecture, circuit architecture, and digital subsystem blocks within power, performance, and area budgets.
- Work with physical-design and DFX teams to deliver complete RTL-to-GDSII designs while improving front-end development flows.
- Co-lead silicon-success methodology, establishing debug practices, bring-up, platform validation, characterization, and path from characterization to production.
- Direct design planning, work breakdown, scheduling, critical paths, talent development, and technical coaching.
What you'll need
- Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering with emphasis on IO subsystems digital/hardware architecture and design.
- Digital IO subsystem IP hardware design and technical engineering management experience leading distributed engineering teams.
- Experience delivering complex digital-on-top IO subsystem IPs through high-volume production tape-outs in advanced FinFET CMOS nodes.
- Technical experience from architecture to implementation of High Speed IO (HSIO) & PHYs digital subsystems, including SerDes and chip-to-chip interconnects.
- Expertise in microarchitecture for low-power, low-latency, high-performance IO datapath between host and peripherals.
- Knowledge of digital design methodologies including clock-domain-crossing checks, reset checks, low-power design, synthesis, static timing analysis, and timing closure.
Nice to have
- Embedded firmware development experience.
Skills: High-Speed IO, SerDes, RTL, Microarchitecture, FinFET
More semiconductor jobs: AMD jobs · Signal integrity jobs · California jobs
This role has been open 0 days — well below the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
250
|
Median days open
71 d
|
Category median salary (all employers)
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (250 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 250 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1536 · 107 employers |
| Median days open | 45 d | 71 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: High-Speed IO, SerDes, RTL, Microarchitecture, FinFET
Who's hiring in this category
- Synopsys · 34 open roles · median 38 d
- AMD (this employer) · 27 open roles · median 47 d
- Cadence Design Systems · 21 open roles · median 142 d
- Qualcomm · 19 open roles · median 71 d
- Micron Technology · 13 open roles · median 43 d
- Apple · 12 open roles · median 27 d
How we counted: 250 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.