Director Applications Engineering PCIE
Originally posted 9 April 2026 by the employer.
About the role
This role leads a team of Application Engineers who partner with customers to integrate Interface IP (IIP) into ASIC SoCs and systems utilizing PCIe and SERDES IPs.
What you'll do
- Lead, hire, and develop a team of Application Engineers to manage customer outcomes, allocating resources across multiple customer programs and internal deliverables. - Own customer escalations for Interface IP integration, managing structured debug and resolution plans alongside R&D, Product, and Program teams. - Define and standardize best practices for pre-silicon integration reviews, signoff checklists, and milestone-based customer engagements. - Direct initiatives to define and implement an AI-empowered flow intended to assist pre-silicon IP integration, debug, and engagement processes. - Coordinate cross-functional feedback loops to improve product quality, documentation, collateral, and enablement based on field learnings. - Track metrics including milestone health, issue trends, response times, and customer satisfaction while monitoring standards such as PCIe and SERDES.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 20+ years of experience in SoC/ASIC development, applications engineering, design, verification, or silicon/IP bring-up, with a background in customer-facing technical leadership. - Experience with high-speed protocols such as PCIe and Ethernet. - Technical depth in Front-End design (RTL/SystemVerilog, CDC/RDC, lint, verification), Back-End implementation (synthesis, STA, place & route, signoff), or Analog/Mixed-Signal design and integration. - Understanding of SoC tape-out flows and milestones, including integration, verification signoff, timing closure, and handoff. - People leadership experience managing hiring, team operating rhythms, and execution across multiple customer programs.
Nice to have
- Experience with High-Speed SerDes development or support.
Skills: SoC/ASIC, customer success, PCIe/Ethernet protocols, simulation, synthesis, STA
This role has been open 197 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 696 |
| Open roles in the wider Physical Implementation family | 108 | 1491 · 109 employers |
| Median days open | 44 d | 71 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: SoC/ASIC, customer success, PCIe/Ethernet protocols, simulation, synthesis, STA
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 152 d
- Synopsys (this employer) · 62 open roles · median 43 d
- Micron Technology · 44 open roles · median 52 d
- GlobalFoundries · 39 open roles · median 26 d
- Qualcomm · 39 open roles · median 76 d
- Keysight Technologies · 34 open roles · median 79 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.