Originally posted 28 October 2026 by the employer.
Lead panel-level fan-out, large-format RDL, and panel-scale packaging for data center and AI accelerators at AMD.
About the role
This role drives panel-scale packaging technology for data center and AI accelerator products through external foundry, OSAT, substrate, materials, and equipment partners. You will own panel-scale technology readiness from concept through qualification and high-volume manufacturing, defining materials, processes, design rules, and DFM/DFY guidelines.
What you'll do
- Define the panel-scale packaging technology roadmap for data center and AI products and align partner technology roadmaps to it. - Lead panel-scale technology development with partners—including panel-level fan-out, large-format RDL, interposers, and panel-scale die bonding—from concept through qualification. - Set technical requirements and guide partners in materials selection and process definition to meet performance, reliability, and cost targets. - Establish design rules and DFM/DFY guidelines with partners using jointly defined test vehicles to validate capability. - Engage partners to resolve large-panel challenges including warpage, dimensional stability, overlay and alignment, and large-area uniformity. - Establish yield and reliability targets, monitor partner data, and drive joint improvement plans through high-volume ramp.
What you'll need
- BS, MS, or PhD in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, Applied Physics, Applied Mathematics, or equivalent. - Proven track record of driving semiconductor technology development through external partners, including foundries and OSATs. - Experience leading cross-functional teams and resolving yield, reliability, and manufacturability challenges.
Nice to have
- Deep knowledge of 2.5D and 3D packaging, with experience in panel-level packaging or large-format substrates. - Experience in wafer-level assembly processes such as fan-out, RDL fabrication, bumping, chip-on-wafer assembly, molding, temporary bonding/debonding, and wafer thinning. - Experience with die bonding technologies including mass reflow, thermocompression bonding (TCB), and hybrid bonding. - Familiarity with emerging panel technologies such as glass-core substrates and panel-level RDL and interposers. - Breadth of experience addressing thermo-mechanical, power delivery, and signal integrity challenges in large, high-power data center packages. - Proven track record qualifying new packaging technologies with partners for advanced data center products and ramping them to high-volume manufacturing.
Skills: panel-level, fan-out, RDL, interposers, hybrid bonding, 2.5D/3D
This role has been open 0 days — well below the 49-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
78
|
Median days open
49 d
|
Median salary
$171k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (78 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 78 |
| Median days open | 36 d | 49 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $171k |
Skills observed across this category: panel-level, fan-out, RDL, interposers, hybrid bonding, 2.5D/3D
Who's hiring in this category
- AMD (this employer) · 12 open roles · median 36 d
- Micron Technology · 10 open roles · median 180 d
- NVIDIA · 7 open roles · median 30 d
- Marvell Technology · 6 open roles · median 26 d
- Broadcom · 4 open roles · median 151 d
- GlobalFoundries · 4 open roles · median 119 d
How we counted: 78 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 26 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.