Digital Signal Processing and System Validation Engineer
Originally posted 17 April 2026 by the employer — open 146 days. Relisted by the employer on 18 August 2026.
This role involves designing digital signal processing blocks for optical data center connectivity products.
About the role
This role involves designing digital signal processing blocks for optical data center connectivity products. You will be responsible for validating the ASIC architecture pre and post-silicon.
What you'll do
- Design digital signal processing blocks for optical data center connectivity products.
- Validate ASIC architecture pre-silicon and post-silicon.
- Translate CDR and equalization architectures into Verilog code for logic synthesis.
- Drive attainment on performance, power, and cost for PAM4 and NRZ design trade-offs.
What you'll need
- MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years of experience in digital signal processing design for SerDes and serial link high-speed data center networking.
- Experience in post-silicon validation of digital and analog mixed-signal IPs.
- Understanding of ADC and analog-based optical and electrical interconnect architectures such as 100G/200G/400G per lane PAM4 and NRZ design trade-offs.
- Experience translating CDR and equalization architectures into Verilog code for logic synthesis.
- Proficient with Matlab, Simulink, and Verilog-HDL/System Verilog coding.
- Experience with front-end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
- Exposure to Design for Test, understanding of scan concept, and writing DFT friendly RTL.
- Experience in synthesis, CDC, static timing analysis.
- Exposure to SDF annotated simulations with understanding of parasitic delays.
Nice to have
- Understanding of high-speed DSP applications and algorithms.
- Experience of high-speed ADC, FFE, DFE, CDR Adaptation algorithms for PAM4 signals.
- Understanding of logic optimization for low power, timing margins & DFT.
- Understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
- Exposure to Verilog AMS simulation, experience in behavioral models of analog circuits.
Skills: digital signal processing, optical data center connectivity, ASIC architecture validation, SerDes, PAM4, NRZ
This role has been open 148 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 11 | 217 |
| Median days open | 142 d | 91 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: digital signal processing, optical data center connectivity, ASIC architecture validation, SerDes, PAM4, NRZ
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom (this employer) · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.