Digital - Principal Systems/DSP Engineer - Bay Area, United States
Originally posted 22 December 2025 by the employer — open 261 days.
About the role
This role involves defining and driving the DSP architecture for 224G and 448G SerDes designs, focusing on best-in-class power, area, manufacturability, and design flexibility for chiplet-based systems.
What you'll do
- Define and architect low-power DSP architectures for 224G PAM4 and 448G SerDes designs.
- Develop and maintain behavioral models of mixed-signal transceiver circuits using MATLAB, Simulink, C, and/or Python.
- Develop, evaluate, and optimize equalization algorithms including FFE, DFE, CTLE, and MLSE/MLSD.
- Architect and evaluate clock and data recovery (CDR) algorithms and loop dynamics.
- Develop and evaluate FEC solutions including inner/outer FEC architectures, RS-FEC (KP4/KP8) integration, and concatenated coding schemes per IEEE 802.3dj and OIF CEI-224G standards.
- Drive silicon bring-up and characterization test plans, correlating pre-silicon system models with post-silicon measurements.
What you'll need
- Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields.
- 10+ years of experience in DSP system architecture and algorithm development for high-speed serial communication systems, with hands-on work at 112G PAM4 or higher data rates.
- Deep expertise in digital communication and signal processing theory, including PAM4 modulation, equalization architectures, CDR loop dynamics, and statistical channel modeling.
- Expert-level proficiency in system modeling using MATLAB, Simulink, C, and/or Python.
- Strong working knowledge of high-speed serial protocols and standards including Ethernet (IEEE 802.3ck/df/dj), PCIe, UCIe, and OIF CEI specifications.
- Detailed knowledge of OIF CEI-224G and IEEE 802.3dj standards including link budget allocation, compliance test methodologies, and FEC performance metrics.
Nice to have
- Experience with chiplet D2D interconnects, optical/electrical interfaces (VCSEL, EML), or DRAM/HBM PHY systems.
Skills: 224G PAM4, 448G SerDes, DSP architectures, equalization algorithms, clock and data recovery (CDR)
This role has been open 77 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Eliyan | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1317 · 100 employers |
| Median days open | 77 d | 91 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: 224G PAM4, 448G SerDes, DSP architectures, equalization algorithms, clock and data recovery (CDR)
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.