Digital IC Design Engineer - Santa Clara, CA, United States
Originally posted 14 April 2026 by the employer — open 149 days. Relisted by the employer on 20 August 2026.
This role focuses on SerDes chips for Audio-Video protocols including DisplayPort and MIPI CSI over CPHY/DPHY.
About the role
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits interfacing to analog circuitry as part of an overall system. You will work on multiple Audio-Video protocols including DisplayPort and MIPI CSI over CPHY/DPHY enabling solutions requiring handling multiple AV streams, video processing, stream encryption, and compression.
What you'll do
- Define architecture and micro-architecture for high-speed SerDes chips.
- Perform RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging of SerDes chips.
- Prepare test methods and specifications.
- Assist in the preparation of application information, data sheets, and demo boards.
- Develop solutions to complex problems through assessment of various techniques and approaches.
- Plan and organize work to ensure timely completion of tasks.
What you'll need
- BSEE with 12 years or MSEE with 10 years of digital/mixed signal ASIC architecture/design experience.
- Successfully taped out multiple devices.
- A thorough understanding of digital logic design.
- Strong understanding of ASIC design flow from RTL to GDSII.
- Familiarity with the Verilog language and simulators.
- A good understanding of analog functionality and exposure to analog IC design methods.
- Ability to solve problems using a systematic approach.
Nice to have
- RTL coding and synchronous/asynchronous digital skills.
- Experience with SystemVerilog.
- Knowledge of simulation tools like Xcelium, code coverage, and debug tools.
- Knowledge of PLL, SerDes, Encoders, Decoders, Video Compression, MIPI Standards, Video Encryption, DisplayPort, I2C, and SPI.
- Synthesis, STA, Lint checkers, Clock domain crossing (CDC) checkers, Logic equivalence checking.
- Scripting skills in Perl, Tcl, Python.
- Familiarity with low power design techniques.
- Knowledge of DisplayPort including HDCP and DSC, MIPI CPHY/DPHY.
- Knowledge of UVM, SystemVerilog, constrained random, and assertion-based verification methodologies.
- Knowledge or experience of FPGA prototyping and Palladium.
- Knowledge of MATLAB.
- Knowledge or experience with physical design flow.
Skills: architecture, micro-architecture, RTL coding, simulation, synthesis, timing closure, SerDes chips
This role has been open 148 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 1 | 217 |
| Median days open | 148 d | 91 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: architecture, micro-architecture, RTL coding, simulation, synthesis, timing closure
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.