Define digital architecture for parallel optical link ASICs built from arrays of microLED transmitters and photodetector receivers.
About the role
Avicena is seeking a Digital Architect to define the digital architecture of a parallel optical link ASIC, including the data path, link management, and calibration and training engines. The role focuses on parallel optical links built from arrays of microLED transmitters and photodetector receivers.
What you'll do
- Define digital architecture and micro-architecture specifications for the data path, link management, and control functions of a parallel optical link ASIC.
- Architect calibration, training, and adaptation engines that set and track analog circuit parameters, partitioning functions between hardware and firmware.
- Define analog/digital interfaces, timing, and control loops with system architects and TX, RX, and clocking leads.
- Define register maps and host control interfaces in collaboration with the firmware team.
- Conduct performance, latency, area, and power trade-off studies.
- Develop architecture models in C/C++, Python, or SystemC to validate algorithms and generate reference data for verification.
- Define clocking, reset, and clock-domain-crossing (CDC) architecture, review RTL and verification plans, and support post-silicon bring-up.
What you'll need
- BS or MS in Electrical or Computer Engineering with 12+ years of digital ASIC design experience, including 5+ years defining architecture or micro-architecture for production chips.
- Deep experience with high-speed link digital design: framing, encoding and scrambling, error detection or FEC, lane deskew and alignment, and link training.
- Experience architecting digital control and calibration for analog/mixed-signal circuits.
- Strong SystemVerilog/Verilog background and understanding of synthesis, timing, and power implications.
- Modeling experience in C/C++ or Python.
- Demonstrated experience in multi-clock design and CDC/RDC architecture.
Nice to have
- Experience with SerDes, die-to-die interfaces (such as UCIe), or optical communication links.
- Background in DSP and adaptation algorithms for communication links.
- Experience with hardware/firmware co-design.
- Expertise in low-power architecture.
- Technical leadership of design teams.
Skills: digital architecture, optical link, micro-architecture, calibration, data path
More semiconductor jobs: SoC design jobs · Sunnyvale jobs
This role has been open 4 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 485 |
| Open roles in the wider Digital Design & Verification family | 4 | 3525 · 120 employers |
| Median days open | 4 d | 79 d (−75 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: digital architecture, optical link, micro-architecture, calibration, data path
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.