$143,800 USD yearly
Originally posted 7 November 2026 by the employer.
About the role
Broadcom's ASIC Products Division is seeking a DFT Lead Engineer to guide DFT programs from chip-level specification through implementation, verification, and production release at the Austin, Texas Development Center. The role covers SoC DFT architecture, test insertion, pattern generation, coverage improvement, and post-silicon debug for designs at 7nm and beyond.
What you'll do
- Define chip-level DFT specifications to meet customer feature requirements and DPPM goals.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and third-party IP integration.
- Collaborate with STA and physical design engineers to achieve DFT mode timing closure.
- Generate, verify, and debug test vectors prior to tape release, and validate test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, yield improvement, and customer-returned part debug on ATE.
- Automate DFT and test vector generation flows using TCL, Perl, Ruby, Python, or C++.
What you'll need
- Bachelor's degree in Electrical, Electronic, or Computer Engineering with 12+ years of experience, or Master's degree with 10+ years of relevant industry experience.
- Background in scan insertion and scan compression using DFT Compiler or Mentor TestKompress.
- Experience with ATPG vector generation, simulation, and debugging using TetraMax or FastScan.
- Hands-on experience with embedded Memory BIST insertion and verification across SRAM, CAM, eDRAM, or ROM.
- Working knowledge of boundary scan standards IEEE 1149.1, IEEE 1149.6, and IEEE 1687 (IJTAG, ICL, PDL).
- Verilog coding, testbench generation, simulation, and scripting capability in TCL, PERL, RUBY, PYTHON, or C++.
Nice to have
- Experience working directly on the ATE.
- Experience with SerDes, DDR, PCIe, ENET, or CXL IOBIST verification and silicon debug.
- Experience working on Tessent SSN.
More semiconductor jobs: Broadcom jobs · DFT engineer jobs
This role has been open 0 days — well below the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
289
|
Median days open
54 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (289 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 289 |
| Open roles in the wider Digital Design & Verification family | 78 | 3524 · 120 employers |
| Median days open | 4 d | 54 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 43 open roles · median 45 d
- Qualcomm · 24 open roles · median 77 d
- NVIDIA · 23 open roles · median 56 d
- Broadcom (this employer) · 21 open roles · median 4 d
- Synopsys · 20 open roles · median 34 d
- NXP Semiconductors · 19 open roles · median 61 d
How we counted: 289 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.