Verification, Validation & Test
About the role
This role involves defining the DFT architecture for a multi-chip system SOC, focusing on test design functions such as Scan, BIST, Memory Repair, and BSD (ACJTAG/DCJTAG).
What you'll do
- Define the DFT architecture for a multi-chip system SOC, including Scan, BIST, Memory Repair, and BSD (ACJTAG/DCJTAG).
- Apply proficiency in Synthesis design constraints (SDC).
- Define and implement OCC.
- Supervise ATPG generation and achieve high coverage goals for scan and at-speed scan.
What you'll need
- Proficiency in Synthesis design constraints (SDC).
- Prior experience with Serializers/Deserializers.
- Sound proficiency in Mentor or Synopsys Test Tools.
- Fluent in RTL level and Gate level simulation.
- Knowledge using synthesis, DFT & Simulation CAD tools.
- Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
- Fluency in scripting in Unix, Perl, Python, and TCL.
- Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
- Knowledge of Verilog and System Verilog.
- Prior experience of multiple tape out in deep submicron 7nm or below.
- Master's Degree or bachelor's degree in EE with a minimum of 15+ years of experience.
Nice to have
- Exposure to advanced DFT techniques like LBIST and streaming.
- Prior Exposure to EMIB architectures and bridge.
More semiconductor jobs: DFT engineer jobs · California jobs
Market context
This role has been open 81 days — well above the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
293
|
Median days open
54 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Eridu AI | All employers we track in this specialty (293 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 293 |
| Open roles in the wider Digital Design & Verification family | 5 | 3525 · 120 employers |
| Median days open | 81 d | 54 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 43 open roles · median 46 d
- Broadcom · 26 open roles · median 5 d
- NVIDIA · 23 open roles · median 57 d
- Qualcomm · 23 open roles · median 81 d
- NXP Semiconductors · 19 open roles · median 62 d
- Synopsys · 19 open roles · median 32 d
How we counted: 293 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.