DFT Engineer (CE-64000920) - Austin, Texas, United States
Originally posted 17 June 2026 by the employer.
About the role
As a DFT engineer in the mixed-signal audio development team, you will perform test planning, insert memory BIST and scan, improve coverage, and deliver test patterns to the product test group. The position supports mixed-signal SoCs for consumer mobile audio markets.
What you'll do
- Define, implement, and review DFT features. - Generate, insert, and verify Memory BIST logic. - Perform scan insertion and ATPG pattern generation. - Develop and review DFT timing and equivalence checking constraints. - Perform MBIST and ATPG pattern verification with gate level simulations, identify test coverage gaps, and perform test cost planning. - Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.
What you'll need
- MSEE with 2+ years of experience or BS with relevant industry experience. - Working knowledge of ASIC DFT design and verification. - Experience with industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, or Test Compiler.
Nice to have
- Experience with Verilog, System Verilog, or VHDL. - Understanding of low power test techniques and architectures. - Knowledge of scripting languages such as Perl, Python, or TCL. - Experience with synthesis, static timing analysis, and developing timing constraints. - Experience with flows and automation. - Experience with debugging and root causing silicon problems.
Skills: DFT features, Memory BIST, scan insertion, ATPG, TetraMAX
This role has been open 127 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 248 |
| Open roles in the wider Digital Design & Verification family | 29 | 3297 · 115 employers |
| Median days open | 127 d | 63 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFT features, Memory BIST, scan insertion, ATPG, TetraMAX
Who's hiring in this category
- AMD · 39 open roles · median 44 d
- Qualcomm · 25 open roles · median 77 d
- NVIDIA · 23 open roles · median 41 d
- NXP Semiconductors · 19 open roles · median 46 d
- Synopsys · 15 open roles · median 29 d
- Intel Corporation · 10 open roles · median 63 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.