DFT Engineer (CE-64000845) - Austin, Texas, United States
Originally posted 28 January 2026 by the employer. Relisted by the employer on 27 October 2026.
About the role
As a DFT engineer in the mixed-signal audio development team, you will perform test planning, insert memory BIST and scan, improve coverage, and deliver test patterns to the product test group. You will support mixed-signal SoCs for consumer mobile audio markets.
What you'll do
- Define, implement, and review DFT features within the development team. - Generate, insert, and verify Memory BIST logic. - Perform scan insertion and ATPG pattern generation. - Develop and review DFT timing and equivalence checking constraints. - Verify MBIST and ATPG patterns with gate-level simulations and resolve test coverage gaps. - Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.
What you'll need
- MSEE with 2+ years of experience or BS with relevant industry experience. - Hands-on working knowledge of ASIC DFT design and verification. - Experience with industry-standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, or Test Compiler.
Nice to have
- Experience with Verilog, SystemVerilog, or VHDL. - Understanding of low-power test techniques and architectures. - Knowledge of scripting languages such as Perl, Python, or TCL. - Experience with synthesis, static timing analysis, and developing timing constraints. - Experience with flows and automation. - Experience with debugging and root causing silicon problems.
Skills: Memory BIST logic, scan insertion, ATPG pattern generation, DFT timing, FastScan, TestKompress, TetraMAX
This role has been open 221 days — well above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
249
|
Median days open
57 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (249 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 249 |
| Open roles in the wider Digital Design & Verification family | 30 | 3359 · 116 employers |
| Median days open | 221 d | 57 d (+164 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: Memory BIST logic, scan insertion, ATPG pattern generation, DFT timing, FastScan, TestKompress, TetraMAX
Who's hiring in this category
- AMD · 36 open roles · median 49 d
- Qualcomm · 25 open roles · median 82 d
- NVIDIA · 21 open roles · median 46 d
- NXP Semiconductors · 19 open roles · median 41 d
- Synopsys · 16 open roles · median 31 d
- Intel Corporation · 10 open roles · median 56 d
How we counted: 249 open DFT Engineering (DFT Test) roles from 54 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.