Originally posted 7 November 2026 by the employer.
About the role
Broadcom's ASIC Products Division (APD) is seeking a DFT Engineer to work on chip-level DFT specification, implementation, verification, and production release at the Austin, Texas Development Center. The role covers SoC DFT activities including test insertion, pattern generation, coverage improvement, post-silicon debug, and yield improvement.
What you'll do
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integration.
- Generate, verify, and debug test vectors before tape release, as well as validate and debug vectors on ATE during silicon bring-up.
- Collaborate with Physical Design, STA, and DI engineers on design closure for test, DFT mode timing closure, and constraints.
- Assist with silicon failure analysis, diagnostics, yield improvement efforts, and debugging customer returned parts on the ATE.
- Code automation and verification scripts using TCL, PERL, RUBY, PYTHON, C++, or similar languages.
- Interface with customers, IP DFT engineers, and globally located physical design and test engineering/manufacturing teams.
What you'll need
- Bachelor's degree in Electrical, Electronic, or Computer Engineering with 5+ years of relevant industry experience, or a Master's degree with 3+ years of relevant industry experience.
- Experience in scan insertion and scan compression using tools such as DFT Compiler, Mentor TestKompress, or SSN.
- Experience with ATPG vector generation, simulation, and debugging using tools like TetraMax or Fastscan.
- Hands-on background in Memory BIST insertion and verification on embedded SRAM, CAM, eDRAM, or ROM.
- Proficiency in boundary scan verification and test vector generation with knowledge of IEEE 1149.1 and IEEE 1149.6, as well as IEEE 1687 (IJTAG, ICL, PDL).
- Verilog coding, testbench generation, and simulation skills, along with a working knowledge of Test-STA.
More semiconductor jobs: Broadcom jobs · DFT engineer jobs
This role has been open 0 days — well below the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
289
|
Median days open
54 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (289 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 289 |
| Open roles in the wider Digital Design & Verification family | 78 | 3524 · 120 employers |
| Median days open | 4 d | 54 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 43 open roles · median 45 d
- Qualcomm · 24 open roles · median 77 d
- NVIDIA · 23 open roles · median 56 d
- Broadcom (this employer) · 21 open roles · median 4 d
- Synopsys · 20 open roles · median 34 d
- NXP Semiconductors · 19 open roles · median 61 d
How we counted: 289 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.