DFT Engineer

Originally posted 6 November 2026 by the employer.

About the role

This role focuses on Design for Test (DFT) implementation from RTL to tapeout for various IPs going into high-performance designs for AI/ML architectures. The focus includes reducing test cost while achieving high coverage, facilitating debug, and enabling yield learning with minimal design intrusion.

What you'll do

• Implement and integrate DFT features, including scan, JTAG, compression, ASST, and MBIST, into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation using Synopsys VCS/Verdi to achieve and maintain test coverage.
• Plan, implement, and verify MBIST, working closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

What you'll need

• BS, MS, or PhD in EE, ECE, CE, or CS with 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• Fluency in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and familiarity with SystemVerilog/UVM.
• Hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• Experience with cross-hierarchy debug and collaborating with design, physical design, verification, and test teams.

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