Originally posted 7 November 2026 by the employer.
About the role
Broadcom's ASIC Products Division (APD) is seeking a DFT Engineer to execute chip-level DFT specification, implementation, verification, and production release at the San Jose, California Development Center. The role covers SoC DFT insertion, pattern generation, coverage improvement, and post-silicon ATE debug across custom ASIC programs.
What you'll do
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Collaborate with STA and physical design teams to achieve design and timing closure for test modes.
- Generate, verify, and debug test vectors prior to tape release, and validate test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, yield improvement, and debug customer returned parts on ATE.
- Interface with external customers and global physical design and manufacturing teams to address test requirements.
What you'll need
- Bachelor's degree in Electrical, Electronic, or Computer Engineering with 5+ years of relevant industry experience, or Master's degree with 3+ years of experience.
- Experience with scan insertion and scan compression using tools such as DFT Compiler, Mentor TestKompress, or SSN.
- Experience in ATPG vector generation, simulation, and debugging using tools such as TetraMax or Fastscan.
- Proficiency in Memory BIST insertion and verification on embedded SRAM, CAM, eDRAM, or ROM.
- Working knowledge of boundary scan standards (IEEE 1149.1 and IEEE 1149.6) and IJTAG standards (IEEE 1687, ICL, PDL).
- Verilog coding, testbench generation, simulation, and scripting capability using TCL, Perl, Ruby, Python, or C++.
More semiconductor jobs: Broadcom jobs · DFT engineer jobs
This role has been open 0 days — well below the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
289
|
Median days open
54 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (289 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 289 |
| Open roles in the wider Digital Design & Verification family | 78 | 3524 · 120 employers |
| Median days open | 4 d | 54 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 43 open roles · median 45 d
- Qualcomm · 24 open roles · median 77 d
- NVIDIA · 23 open roles · median 56 d
- Broadcom (this employer) · 21 open roles · median 4 d
- Synopsys · 20 open roles · median 34 d
- NXP Semiconductors · 19 open roles · median 61 d
How we counted: 289 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.