DFT Architect

Lead Design-for-Test strategy for complex ASIC/SOC designs.

About the role

This role involves leading Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes, driving end-to-end DFT architecture including scan with compression technologies, MBIST, boundary scan, SSN architecture, functional testing, and at-speed test methodologies.

What you'll do

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
• Lead implementation of scan insertion, ATPG, MBIST, boundary scan, SSN implementation, and test compression methodologies.
• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
• Analyze and resolve DFT-related timing, routing, and testability challenges.
• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.

What you'll need

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 10+ years of experience in ASIC/SOC DFT implementation and architecture.
• Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies.
• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
• Strong understanding of RTL design, timing, physical design constraints, and silicon debug.
• Experience with advanced technology nodes and large SOC integration.
• Strong scripting and automation skills using Tcl, Python, Perl, or Shell.

Nice to have

• Experience with automotive safety standards such as ISO 26262.
• Exposure to chiplet-based architectures and 3D IC testing methodologies.
• Knowledge of diagnosis-driven yield improvement and silicon analytics.

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