Design Verification Engineer - USA-CA San Jose Innovation Drive, United States
$143,800 - $230,000 USD yearly
Originally posted 19 June 2026 by the employer.
Verification environment development and subsystem verification using SystemVerilog and UVM.
About the role
Broadcom's ASIC Product Division is seeking a Design Verification Engineer to support SoC and embedded IP development programs. The role focuses on advanced subsystem and block-level verification to meet customer requirements.
What you'll do
- Develop verification environments using SystemVerilog and UVM. - Design verification components including UVM agents and behavioral models. - Implement coverage models and assertions using SystemVerilog. - Develop random and directed test cases against design specifications. - Analyze and debug simulation failures and evaluate coverage results. - Resolve complex verification trade-off scenarios across system and sub-block levels.
What you'll need
- Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent. - 12+ years of relevant industry work experience. - Experience verifying designs at the system level and block level. - Fluent knowledge of RTL verification methodologies including SystemVerilog. - Strong experience in ASIC design verification flows and DV methodologies. - Strong working knowledge of object-oriented verification languages (such as UVM and OVM), C/C++, Perl, and scripting.
Nice to have
- Experience with hardware design and debug, C++/SystemC, and other programming languages. - Experience working with emulators and FPGA-based prototyping. - Familiarity with overall chip design methodologies and tools. - Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.
Skills: SystemVerilog, UVM, ASIC verification, coverage, assertions
This role has been open 125 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1241 |
| Open roles in the wider Digital Design & Verification family | 52 | 3297 · 115 employers |
| Median days open | 66 d | 65 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, ASIC verification, coverage, assertions
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.