Design Verification Engineer, New Grad - San Jose, California, United States
$120,000 - $150,000 USD yearly
Originally posted 27 October 2026 by the employer.
Verify chip-level control and initialization for SambaNova's Reconfigurable Dataflow Unit (RDU).
About the role
As a new grad Design Verification Engineer, you will write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You will run regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out.
What you'll do
- Write and execute verification plans for chip-level control and initialization features. - Build SystemVerilog and UVM testbench components, including sequences, checkers, assertions, and functional coverage. - Write directed and constrained-random tests to find corner cases. - Debug simulation and regression failures with RTL designers. - Analyze functional and code coverage and close coverage gaps.
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - Coursework or project experience in digital design and computer architecture. - Experience with SystemVerilog or Verilog. - Scripting experience in Python, Perl, TCL, or shell. - Experience with UVM. - Familiarity with constrained-random verification, functional coverage, and assertions. - Familiarity with clock domain crossing concepts.
Nice to have
- M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - Experience using AI tools such as Claude for verification development and debug. - Internship experience in design verification.
Skills: SystemVerilog, UVM, constrained-random, assertions, coverage
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1277 |
| Open roles in the wider Digital Design & Verification family | 6 | 3362 · 116 employers |
| Median days open | 69 d | 64 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, constrained-random, assertions, coverage
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.